Registers and the Fetch–Decode–Execute Cycle

AQA 4.6.1 — Registers and the Fetch–Decode–Execute cycle

Retrieval: the previous lesson named the Control Unit, ALU, registers and buses, and described Fetch–Decode–Execute as three stages in outline. This lesson opens each stage up in detail — which specific register holds what, and exactly what moves where, one step at a time.

Key vocabulary

Program Counter (PC) — always holds the memory address of the next instruction to be fetched.
Memory Address Register (MAR) — holds the address currently being read from or written to in memory.
Memory Data Register (MDR) — holds the actual data or instruction that memory just returned (or is about to store).
Current Instruction Register (CIR) — holds the instruction currently being decoded and executed.
Accumulator (ACC) — a general-purpose register the ALU uses to build up the result of a calculation.

Understand — why several small registers, not one

Each register has one narrow job so the CPU never has to guess what a value in it means: the PC is only ever "the next address to fetch", never data; the MDR is only ever "whatever memory just handed back". Separating these roles is what lets the Control Unit coordinate the cycle reliably, cycle after cycle, without ambiguity about what's currently held where.

Visualise — registers and buses around the CPU

        Address bus
   MAR ───────────────▶  ┌────────┐
                          │ Memory │
   MDR ◀───────────────  └────────┘
        Data bus
    │
    ▼
   CIR ──▶ Control Unit ──▶ ALU ──▶ ACC
    ▲
   PC (holds the address that gets copied into MAR each fetch)

The address bus carries only addresses (MAR → memory); the data bus carries the actual instruction or value (memory ↔ MDR); the control bus (not pictured) carries signals like "read" or "write" that tell memory which direction data should flow.

Trace it — one full cycle, register by register

Tracing what PC=0 holding the instruction ADD 5 (add the value at address 5 to the accumulator) actually does:

Step	PC	MAR	MDR	CIR	Action
Start	0	–	–	–	–
Fetch	0 → 1	0	`ADD 5`	`ADD 5`	PC's address is copied to MAR; memory returns the instruction into MDR; PC increments immediately, ready for next time; MDR's content is copied into CIR
Decode	1	5	–	`ADD 5`	The Control Unit reads CIR and recognises "ADD", then places the operand's address (5) into MAR
Execute	1	5	value at 5	`ADD 5`	Memory returns the value stored at address 5 into MDR; the ALU adds it to ACC

Explain — why PC increments during Fetch, not later

The Program Counter increments as part of Fetch, straight after the instruction's address is used — before Decode or Execute even begin. This matters because some instructions (like JUMP) deliberately overwrite PC again during Execute to send the cycle somewhere else entirely. If PC only incremented at the very end, a jump's new address would just get overwritten right back to "next instruction as normal" — incrementing early is exactly what makes jumps able to work.

Common mistake

Confusing MAR and MDR: MAR holds an address (a location), MDR holds the value found at that location. They're used together in sequence — MAR says where, then MDR receives what — never the other way round.

Check your understanding

A CPU is about to fetch the instruction at address 8. What goes into MAR first, and what does MDR contain immediately afterwards? (MAR receives 8, copied from PC, before memory is read. MDR then receives whatever instruction is actually stored at address 8, once memory responds.)

Challenge

Trace this 4-instruction program by hand, listing the PC value at the start of each step, for 6 steps total: instruction 0 is LOAD A, instruction 1 is ADD B, instruction 2 is STORE C, instruction 3 is JUMP 1. What PC values do you visit, in order, and why does the sequence repeat?

Looking ahead: the next lesson (Processor Performance) asks how fast a CPU can run through cycles like this one, over and over — and why some CPUs get through far more of them per second than others.